1. Field of the Invention
The present invention relates to a method for operating a non-volatile memory cell, and more particularly to a method for programming an electrical programmable read only memory (EPROM) cell at low operation voltages.
2. Description of the Prior Art
Single-poly electrical programmable read only memory (EPROM) devices or one-time programmable (OTP) read only memory devices are known in the art. A single-poly EPROM cell is a non-volatile storage device, which is fabricated using process steps that are fully compatible with conventional single-poly CMOS fabrication process steps. As a result, single-poly EPROM cells are often embedded in CMOS logic and mixed-signal circuits.
To save battery power of portable devices, low-voltage operations for EPROM are desired. Prior art such as U.S. Pat. No. 5,761,126 filed Feb. 7, 1997 by Chi et al. entitled “Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell” discloses a single-poly EPROM cell that utilizes a reduced programming voltage to program the cell. The layout and the programming voltage of the single-poly EPROM cell are reduced by eliminating the N+ contact region which is conventionally utilized to place a positive voltage on the N-well of the cell, and by utilizing a negative voltage of 6V˜7V to program the cell. The negative voltage is applied to a P+ contact region formed in the N-well, which injects electrons directly onto the floating gate of the cell.
U.S. Pat. No. 6,130,840 filed Apr. 28, 1999 by Bergemont et al. entitled “Memory cell having an erasable Frohmann-Bentchkowsky memory transistor” discloses a memory cell having an erasable Frohmann-Bentchkowsky P-channel memory transistor and an N-channel MOS access transistor. Eraseability is provided by utilizing a P-well which is formed adjacent to the memory transistor, and a floating gate which is formed over both the channel of the memory transistor and the P-well. With a physical gate length of 0.35 microns based on a 0.35-micron design rule, an operation voltage of 5.75 volts is applied to well and source region of the memory cell.
U.S. Pat. No. 6,509,606 filed Apr. 1, 1998 by Merrill et al. entitled “Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process” discloses a single-poly EPROM cell that does not incorporate oxide isolation and thereby avoids problems with leakage along the field oxide edge that can lead to degraded data retention. Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region.
However, conventional methods for programming the single-poly EPROM are still operated at voltages that are relatively higher than Vcc (input/output supply voltage), for example, a high voltage of about 5˜7V that is higher than typical Vcc=3.3V, thus requiring additional high-voltage circuitry and high-voltage devices thereof. Further, conventional single-poly EPROM technology needs a large cell size and a high voltage to capacitively couple the floating gate for programming the memory cell.